Embodiments of the inventive subject matter relate to the field of integrated circuits, and more particularly to methods for processing scan chains in integrated circuit.
Some integrated circuit (IC) technologies use scan-based design methodologies and techniques to facilitate design, testing, and diagnostics. In scan designs, especially full scan designs, sequential circuits are converted into combinational circuits via scannable latches or flip-flops during testing or for configuration purposes (e.g., for temperature sensor calibration data). Using a scan-based design, structural testing may be more controllable and observable. Another aspect of using scan designs is that the test cost is less than functional testing, especially for submicron designs. Scan-based design can also be used to provide separate means to access logic in the functional data path of an IC.
For example, boundary scan is a method for testing interconnects (wire lines) on printed circuit boards or sub-blocks inside an integrated circuit. Boundary scan is also widely used as a debugging method to watch integrated circuit pin states, measure voltage, or analyze sub-blocks inside an integrated circuit. In the 1980s, the Joint Test Action Group (JTAG) developed a specification for boundary-scan testing that was standardized in 1990 as the IEEE standard 1149.1-1990. In 1993 a new revision titled 1149.1a was introduced. Another approach is the IBM LSSD (Level-Sensitive Scan Design) boundary scan methodology.
The boundary-scan test architecture adds a boundary-scan cell that includes a multiplexer and latches to each pin on the device. Boundary-scan cells in a device can capture data from pin or core logic signals, or force data onto pins. Captured data is serially shifted out and externally compared to the expected results. Forced test data is serially shifted into the boundary-scan cells. All of this is controlled from a serial data path called the scan path or scan chain. For normal operation, the added boundary scan latch cells are set so that they have no effect on the circuit, and are therefore effectively invisible. However, when the circuit is set into a test mode, the latches enable a data stream to be shifted from one latch into the next. Once a complete data word has been shifted into the circuit under test, it can be latched into place so it drives external signals. Shifting the word also generally returns the input values from the signals configured as inputs.
In many server computer systems, scan chains are also used to initialize and monitor all system latches of chips, such as processors during functional and test modes. However, after all chips are initialized and working correctly, system latches can be changed to improper settings via scan chains, such as by applying scan chains accidentally or by incorrect settings in a scan chain. In some cases, configuration settings are manipulated in order to circumvent security mechanisms. The following chip settings should be protected from such unintended changes in order to avoid system malfunctions and damages:                mode settings (to enable/disable certain units/chiplets on a chip);        fence settings (to hide access to certain areas on chip);        clock/PLL (Phase-Locked Loop) settings (to allow only change of clock ratios/PLL settings for certified persons).        